The present invention relates to the field of integrated circuit binary adders and in particular to binary adders employing a segmented propagation path.
2. Description of the Prior Art
The addition of multiple-bit binary numbers can be implemented two ways. First, the arithmetic operations can be performed serially, i.e., each order of bits is added in sequential order. The alternate method is parallel addition, in which each order of bits is added simultaneously. In a parallel adder, a full adder is usually required for each order of bits to accept a possible carry from the proceeding stage or order of bits. The serial binary adder requires only one adder. Data bits are shifted serially into and out of the adder by means of shift registers. Arithmetic operations in a serial adder are usually slower than in a comparable parallel adder. Even though only one adder is used, an obvious disadvantage of a serial adder is that three shift registers are required, i.e., two input shift registers and an output shift register. Ripple through or asynchronous adders are parallel adders which operate on each binary pair of bits while the carry bit is serially transferred to the next stage. Thus, the second pair of bits must wait until the addition of the first pair of bits is completed. This results in a delay in the carry input to the seond and following adders and a delay in the output of the sum carry-out bit. Typically, a carry look ahead principle is employed in parallel adders. The principle of carry look-ahead is to examine a number of stages of inputs for each of these stages. Each carry is then applied to the adder corresponding to the appropriate bit. The addition of the carry then produces the proper sum. The circuit complexity of parallel full adders increases as the number of bits manipulated by the full adder is increased. For example, Texas Instrument SN 7483A is a four bit binary full adder and employs a minimum of 36 gates to perform the addition of two four bit numbers. Thus, multiple bit binary numbers exceeding four orders must be serially combined. Each four bit adder must wait for the carry out of the proceeding adder before performing its operation. This configuration entails both relatively slow circuit speeds and large amounts of silicon chip area.
A double propagation line adder has been devised and is disclosed in a related U.S. Pat. No. 4,031,379 issued June 21, 1977. The addition is neither strictly serial nor parallel but employs the concept of a logical propagation line. The present invention differs in that it employs a single propagation line.